NUS - Wei Li is Hiring

Outline

• About Myself
• What Is My Research About?
• Research Directions: better solvers, autonomous EDA, robust AI hardware, and future hardware.
• What I Can Provide: industry path, academic path, and AI research bridges.
• Who Should Reach Out?
• How to Contact Me

About Myself

I am a Ph.D. candidate at Carnegie Mellon University, advised by Prof. Shawn Blanton and Prof. Jose Moura. Before CMU, I received my B.Sc. and M.Phil. from The Chinese University of Hong Kong, advised by Prof. Bei Yu and Prof. Michael R. Lyu.

I was named a 2026 ML and Systems Rising Star, and received the Croucher Fellowship, Apple Ph.D. Fellowship in Integrated Systems twice, and the Qualcomm Innovation Fellowship. My work has received Best Paper Awards at ASP-DAC, ISSTA, and ICTAI, plus a Best Paper Honorable Mention at ICLAD.

My research sits at the intersection of design automation, hardware testing, and AI. In one sentence: I want to build intelligent design automation and testing systems that make chip development faster, more reliable (and maybe a little less soul-crushing).

What Is My Research About?

We are now in the era of AI. I am very excited about it. The demand for AI hardware is increasing rapidly, but hardware development is struggling to keep up with the speed of AI architecture evolution.

AI demand is accelerating, while chip development remains slow, expensive, and human-intensive. For your reference, USD 667B is roughly FOUR entire NBA leagues.

AI architectures move fast; hardware support often arrives years later. This lag is exactly the kind of gap I want my group to attack.

The basic reason is simple to say (and painful to live with): a modern chip can require years to move from an abstract specification to manufacturable silicon. The design problem is too complex to solve in one shot, so the industry divides it into many stages: architecture, RTL, verification, synthesis, floorplanning, placement, routing, timing closure, testing, diagnosis, and more. Divide-and-conquer is beautiful, but it also creates boundaries.

Engineers often discover violations late, only to realize that the fix belongs to an earlier stage. Communication across teams and stages can be measured in days or weeks. For the most ambitious chips, the timeline can be around two years and involve more than one thousand engineers when the target is optimal performance, power, and area (PPA).

Imagine you design a brilliant architecture that is friendly to agentic AI today. In a conventional high-end chip flow, turning it into competitive silicon can still mean roughly two years, 1000+ engineers, and many rounds of painful iteration.

The first two directions ask how to design chips faster. The third asks how to trust the chips after they enter real AI infrastructure. The fourth asks what happens when the substrate itself changes, from 2D silicon toward new computing fabrics.

The timing is almost unreasonable: the problems are hard, the industry needs answers, and the next generation of students can still leave fingerprints on the field (yes, I mean this quite seriously). Let us try to build something that people will remember.

Research Directions

1. Better Solvers for Each Stage

This direction is a good fit if you are interested in an industrial research path, and if you like optimization, AI, algorithms, data structures, or CS theory. Many EDA subproblems can be abstracted into beautiful mathematical problems. Generations of researchers have proposed elegant algorithms and data structures, from classical heuristics and analytical methods to specialized data structures such as dancing links for multiple patterning layout decomposition. This is why I fell in love with research as an undergraduate: the elegant algorithms you learned from textbooks can quietly live inside almost every electronic device you use every day (hard to imagine a more romantic job for an algorithm, right?).

A recurring challenge is the "impossible triangle" among quality, runtime, and generalizability. In recent years, new methods have become especially exciting: reinforcement learning and graph learning for AI4EDA, and differentiable programming for optimization problems that can be integrated naturally into deep learning toolkits and accelerated on AI hardware.

Differentiable optimization is just similar to training a neural network.

A nice feedback loop appears here: AI hardware accelerates AI-friendly EDA algorithms, and these algorithms can help produce better AI hardware (cool, right?). Related examples from my work include graph learning for layout decomposition, point-cloud learning for routing tree construction, and differentiable global routing.

2. Autonomous EDA Flows with LLMs

Advancing individual solvers is necessary, but not sufficient. Closing the gap between AI hardware demand and chip design capacity requires a paradigm shift in how the entire flow operates. Today, design flows involve repeated failure, rollback, script writing, debugging, and human coordination. LLMs create a new chance to automate script generation, RTL coding, verification assistance, design-space exploration, and flow management.

But chip design is not a normal software-agent playground. It is large-scale, multimodal, tool-heavy, and full of hard physical constraints. How can an LLM understand RTL text, graphs, layouts, timing reports, waveforms, tool logs, and design intent without getting lost? How should it plan, call tools, verify progress, and know when to ask humans for help?

I do not view LLMs only as an application to chip design. I view chip design as one of the best arenas for testing the real capability of LLM agents: the system is among the most complex artifacts humans build, and improvement can affect industry immediately. My recent BRIDGE work is one step in this direction: connecting graph-structured chip data with LLM reasoning. The rise of companies such as Ricursive Intelligence and Agentry also shows how hot this vision has become.

3. Robust AI Hardware and Silent Data Corruption

No product can be guaranteed flawless forever, and chips are no exception. With the explosive deployment of AI infrastructure, industry has observed a severe and unexpected failure mode: chips can pass production tests, enter datacenters, and later produce wrong results without warning. This is known as silent data corruption (SDC).

This problem has drawn major industrial attention; see, for example, Silent Data Corruption at Scale and Silent Data Corruption by 10x Test Escapes Threatens Reliable Computing. In my lab at CMU, we have been collaborating with multiple large technology companies and chip organizations on testing, diagnosis, and reliability.

Open questions include: if SDC is caused by escaped defects, why do those defects escape manufacturing test, and how can we detect more of them before shipping? If defects arise or become visible after deployment, how can AI systems become robust to them? Can we design cheap, efficient, and scalable in-field tests for new defects before they silently damage training or inference?

My early work on SDC from a fault-model perspective: we worked with industry, collected thousands of failure cases, and observed that the traditional fault model used in industry matched only about 5% of them.

What I Can Provide

Industrial Path

I have close relationships with industrial EDA and testing teams, especially in the U.S. semiconductor ecosystem. I received Apple Ph.D. Fellowship support twice and the Qualcomm Innovation Fellowship, and I interned in core design automation research teams at Apple and NVIDIA. I also maintain active connections around testing and reliability with teams connected to Intel, Google, Broadcom, and others.

I also know founders and early members of new AI-for-chip-design startups, including Ricursive Intelligence and Agentry. I have referred and recommended several mentees and friends into related companies, and I will be very serious about helping my students find good internships, collaborators, and industrial impact when that is the path they want.

Academic Path

I also come from a strong EDA and testing academic lineage. My CMU advisors are Prof. Jose Moura, former IEEE President and a widely respected scholar, and Prof. Shawn Blanton, a leading researcher in hardware testing. My CUHK M.Phil. advisor Prof. Bei Yu is one of the most visible EDA researchers, with deep industrial impact. My thesis committee member, collaborator, and referee Prof. Subhasish Mitra at Stanford is a leading figure in resilient computing and future chip systems.

I have also learned from and collaborated with Prof. Michael R. Lyu, Prof. Lingming Zhang, Prof. David Pan, and many others. If you hope to continue in academia, I will do my best to help you build taste, publish strong work, meet the right people, and grow into an independent researcher.

This network is not limited to traditional EDA. I also have resources for students who want to do serious AI research, not only AI as a buzzword taped onto chips. For example, Zhengyang Geng, a good personal friend and a Ph.D. student at Carnegie Mellon University advised by Prof. Zico Kolter and working closely with Prof. Kaiming He, is one of the strongest young scholars I know on one-step generation. I see great opportunities to bring one-step generation into the chip world, and I am very happy to serve as a bridge between students in my group and these AI researchers.

A snapshot of academic and industrial collaborators around my research.

Who Should Reach Out?

Please reach out if you are a prospective Ph.D. student, master's student, undergraduate researcher, or visiting student who is excited by one or more of the following:

• EDA, chip design automation, physical design, RTL, verification, or testing.
• AI for EDA, graph learning, reinforcement learning, differentiable optimization, or LLM agents.
• Hardware reliability, diagnosis, silent data corruption, and robust AI systems.
• Future hardware such as photonics, compute-in-memory, 3D integration, and post-von-Neumann architectures.

You do not need to already know EDA (and please do not be scared by these terms!). Some of my favorite students are people who arrive from AI, algorithms, systems, or architecture, then discover that chips are an absurdly good playground for their taste (including me: my undergraduate major was computer science, and I knew almost nothing about EDA or testing before I started research). TBH, I even believe chips are one of the most promising directions from a very practical point of view (great industry jobs, faculty opportunities, and, if we are lucky and stubborn enough, a real chance to leave your name somewhere in the history of computing). What matters most is curiosity, discipline, and the courage to work on problems that are larger than one person.

How to Contact Me

If you are interested, please email me at werry715@gmail.com. A helpful email includes your CV, transcript if available, a short description of your research interests, and one or two projects or papers that made you curious. You can also mention whether you are looking for Ph.D. admission, master's research, undergraduate research, or a visiting opportunity.