Circuit Fusion Read Note

Circuit Fusion

Basic idea: learn a fusion circuit embedding by fusing different modalities: RTL code, function description, netlist graph, RTL AST.

Data

41 RTL designs - 7,166 RTL sub-circuits - generating same function 57,328 sub-circuits (Each with 8 sub-circuits)

summary - coming from GPT4 (prompt input is the verilog code)
code - existing
graph - obtained by code. nodes are operators.

How circuit is divided into sub-circuits?

Training details

Intra-modal learning

1. mask circuit graph nodes (operators, e.g., AND, XOR, MUX) and predict the masked nodes
2. intra-modal contrastive learning: positive sample - sub-circuits with the same functionality
   1. Q: How to create same functionality and ensure it is correct? A: using open-source tools, Yosys and ABC

Cross-modal alignment

Multi-modal fusion

1. Mask summary modeling

Query: Masked summary embedding (randomly masking parts of high-level summary)

Key, Value: Mix-up of code-graph

Q: why not simply mix-up everything and feed into a transformer (self-attention)

2. Summary and mix-embedding matching

Alignment w. Netlist - RTL

What is RAG inference here?

Evaluation: what tasks?

1. predicting slack for each individual register (sub-circuit level)

slack calcuation example (thanks deepseek)

假设一个设计中：

目标时钟周期：1ns（1GHz）

组合逻辑延迟：0.7ns

寄存器Setup Time：0.1ns

CLK to Q
D input
Q OUTPUT

时钟Skew：0.05ns

计算Setup Slack：

Copy
Slack = (1ns - 0.05ns) - (0.7ns + 0.1ns) = 0.95ns - 0.8ns = 0.15ns  
Slack为正，满足时序要求。若组合逻辑延迟增加到0.9ns，则Slack为-0.05ns（时序违例）。

1. worst negative slack (WNS) prediction
2. total negative slack (TNS) prediction
3. power prediction
4. area prediction

The four above is circuit level

Q: how to use sub-circuit emebeddings to do circuit level predictions? Concat? If concat, how to handle the number of sub-circuits that changes for each design? A: They add them up. And then concat with some design-level features (what is included in their exp), and then use a regression model.
Q: This compares with SNS v2, but it seems to not publish the code?

Note: in circuit-level tasks, they include design level features, e.g., number of different operator types. We need to figure out what features they use.